Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device which generates a column select signal in response to a column command signal and performs data input/output operations using the generated signal.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) has at least tens of millions of memory cells for storing data, and the semiconductor memory device stores or outputs data in accordance with a command from a control unit, for example, a CPU. For example, when the CPU requests a write operation, data is stored in a memory cell corresponding to an address inputted from the CPU and, when the CPU requests a read operation, data stored in a memory cell corresponding to an address inputted from the CPU is outputted. During the write operation, data inputted through an input/output pad is inputted to the corresponding memory cell via a data input path. During the read operation, data stored in the corresponding memory cell is outputted to the outside through the input/output pad via a data output path.
FIG. 1 illustrates general read and write operations of a semiconductor memory device. For reference, tens of millions of memory cells may be inside a semiconductor memory device. However, for convenience of explanation, only one memory cell is illustrated and reference numeral 110 is designated thereto.
A read operation of the semiconductor memory device will be described briefly with reference to FIG. 1.
When a word line WL selected by decoding an inputted row address is enabled, a cell transistor T1 of the memory cell 110 is turned on, and data stored in a cell capacitor C1 is charge-shared with a bit line BL, which has been precharged, to be substantially equal to a voltage level of a bit line /BL. Through the charge-sharing operation, the bit lines BL and /BL come to have a slight potential difference. For reference, the level of the precharged voltage may correspond to half the level of a core voltage which is an internal voltage.
A bit line sense amplifier 120 may sense and amplify a slight potential difference between the bit lines BL and /BL. In other words, if the potential of the bit line BL is higher than the potential of the bit line /BL, a voltage of the bit line BL may be amplified to a pull-up voltage RTO, and a voltage of the bit line /BL may be amplified to a pull-down voltage SB.
Meanwhile, when a column select signal YI selected by decoding a column address inputted in accordance with a column command signal is activated, a transistor of a column selection unit 130 may be turned on to connect the bit lines BL and /BL to segment input/output lines SIO and /SIO), respectively. That is, data amplified in the bit line BL may be transferred to the segment input/output line SIO, and data amplified in the bit line /BL is transferred to the segment input/output line /SIO.
A transistor of an input/output switching unit 140 is turned on in response to an input/output control signal CTR_IO corresponding to the column address, and the segment input/output lines SIO) and /SIO are connected to local input/output lines LIO and /LIO, respectively. That is, the data transferred to the segment input/output line SIO may be transferred to the local input/output line LIO, and the data transferred to the segment input/output line /SIO may be transferred to the local input/output line /LIO. Finally, a read driving unit 150 may drive a global input/output line GIO, depending on the data transferred through the local input/output lines LIO and /LIO.
In summary, data stored in the memory cell 110 may be transferred from the bit lines BL and /BL to the segment input/output lines SIO and /SIO in response to the column select signal YI, and the data transferred to the segment input/output lines SIO and /SIO may be transferred to the local input/output lines LIO and /LIO in response to the input/output control signal CTR_IO. The data transferred to the local input/output lines LIO and /LIO may be transferred to the global input/output line GIO by the read driving unit 150. The data transferred in this manner may be finally outputted to the outside through a corresponding input/output pad (not shown).
On the other hand, data inputted from the outside during a write operation may be transferred in a direction opposite to that of the read operation. That is, data applied through the input/output pad may be transferred from the global input/output line GIO to the local input/output lines LIO and /LIO through a write driving unit 160, from the local input/output lines LIO and /LIO to the segment input/output lines SIO) and /SIO, and from the segment input/output lines SIO and /SIO) to the bit lines BL and /BL. The data transferred in this manner may be finally stored in the memory cell 110.
FIG. 2 is a block diagram illustrating a circuit for generating the column select signal YI of FIG. 1, specifically, a source signal generation unit 210 and a column decoding unit 230.
The source signal generation unit 210 is configured to generate a source pulse signal AYP having a constant pulse width in response to a read command RD activated during a read operation and a write command WT activated during a write operation in accordance with an external command. In general, the pulse width of the source pulse signal AYP may be determined based on an external clock signal.
The column decoding unit 230 is configured to decode an external column address ADD and generate a column select signal YI having a pulse width corresponding to the source pulse signal AYP. Here, the column select signal YI may refer to a signal activated in accordance with a result of decoding ‘n’ column addresses ADD.
FIG. 3 is a timing diagram illustrating an operation of the circuit illustrated in FIGS. 1 and 2.
Referring to FIGS. 1 to 3, when an active command ACT is applied, the corresponding word line WL may be enabled, and the bit lines BL and /BL may come to have a slight potential difference depending on the stored data. As mentioned above, the bit line sense amplifier 120 may sense and amplify the slight potential difference between the bit lines BL and /BL. When a read command RD or a write command WT is applied after a RAS (Row Access Strobe) to CAS (Column Access Strobe) delay tRCD, the column select signal YI may be activated after a period of time, and the bit lines BL and /BL and the local input/output lines LIO and /LIO may be connected together to transfer data. Here, a minimum value of the tRCD may be defined according to a point of time when the column select signal YI can be activated after the voltages of the bit lines BL and /BL are sufficiently amplified.
A semiconductor memory device may successively receive read and write commands RD and WT, which are column command signals. In this regard, a time interval between successive CAS (Column Access Strobe) signals may be referred to as tCCD (i.e., tCCD is a CAS to CAS Delay). In a semiconductor memory device, lines for transferring data may be precharged to a constant voltage. The time tCCD may be related to this requirement, and may be defined as a time interval from a time at which one column select signal YI is activated to transfer data, to a time at which the next column select signal YI is activated to transfer data after respective lines are precharged again. For stable data transfer, a stable precharging operation may be completed within the time tCCD.
FIGS. 4A and 4B are timing diagrams illustrating circuit operation of a conventional semiconductor memory device, based on the tRCD. The tRCD may have minimum and maximum values. Here, the minimum value refers to the earliest time when a column select signal YI can be activated, and the maximum value refers to the latest time when a preceding (first) column select signal YI can be applied while the time tCCD is secured with reference to a second column select signal YI.
FIG. 4A shows a case in which the tRCD has the maximum value.
Referring to FIGS. 3 and 4A, data of the bit lines BL and /BL may be amplified after the input of an active command ACT. Then, the column select signal YI (a first YI) may be activated, and the data of the bit lines BL and /BL may be transferred to the local input/output lines LIO and /LIO. After the tCCD, the next column select signal YI (a second YI) may be activated, and data of the bit lines BL and /BL may be transferred to the local input/output lines LIO and /LIO.
FIG. 4B shows a case in which the tRCD has the minimum value.
Referring to FIGS. 3 and 413, after the input of the active command ACT, the column select signal YI may be activated earlier than in the case of FIG. 4A. Even when the column select signal YI may be activated at the minimum value of the tRCD, data of the bit lines BL and /BL may be transferred to the local input/output lines LIO and /LIO. A factor to be considered in this regard is the pulse width of the column select signal YI If the pulse width of the column select signal YI is too small, there is a possibility that an amplification operation of the bit lines BL and /BL will become insufficient, Therefore, the column select signal YI may have a relatively large pulse width.
Referring again to FIG. 2, the pulse width of the column select signal YI in the case of a conventional semiconductor memory device may be the same as the source pulse signal AYP. That is, the column select signals YI shown in FIGS. 4A and 4B have the same pulse width of t1. In this case, the pulse width of the column select signals YI may be designed for a case in which the tRCD has a minimum value. In other words, all column select signals YI have a relatively large pulse width of t1. In order to guarantee an acceptable amplification operation when the tRCD has a minimum value, it may be necessary to set a relatively large pulse width of the column select signals YI.
However, when column select signals YI have a large pulse width, a sufficient precharging time may not be guaranteed in the time tCCD. In other words, the time tCCD between deactivation of a column select signal YI (a first YI) and activation of the next column select signal YI (a second YI) may be too short to guarantee sufficient completion of a precharging operation. Failure to secure a sufficient precharging time means that a stable data transfer operation of the semiconductor memory device may not be guaranteed.